#pragma pack(4)
typedef struct GeneralHeaderUL
{
  uint32_t NewFlag;
  uint16_t SFN;
  uint16_t SubframeN;
} GeneralHeaderUL;

typedef struct GeneralHeader12
{
  uint32_t NewFlag;
  uint16_t SFN;
  uint16_t SubframeN;
} GeneralHeader12;

typedef struct UE_UL_TYPE1_PUBLIC_C
{
		uint32_t PRACHOffset;  //yihuan add 20180611
    uint32_t PUCCHCOffset; //yihuan add 20180620
    uint32_t PUCCHDOffset; //yihuan add 20180620
    uint32_t PUSCHCOffset;
		uint32_t PUSCHDOffset;
}UE_UL_TYPE1_PUBLIC_C;

typedef struct UEULPHYADPtoPHYType1
{
  GeneralHeaderUL GHead;
  UE_UL_TYPE1_PUBLIC_C UL_TYPE1_PUBLIC_C;
} UEULPHYADPtoPHYType1;

//yihuan add 20180611
typedef struct UE_UL_TYPE1_PRACH
{
 /// Preamble index for PRACH (0-63)
  uint8_t ra_PreambleIndex;
  /// RACH MaskIndex
  uint8_t ra_RACH_MaskIndex;
  /// Target received power at eNB (-120 ... -82 dBm)
  int8_t ra_PREAMBLE_RECEIVED_TARGET_POWER;
  /// PRACH index for TDD (0 ... 6) depending on TDD configuration and prachConfigIndex
  uint8_t ra_TDD_map_index;
  /// Corresponding RA-RNTI for UL-grant
  uint16_t ra_RNTI;
  /// Parameter: prach-ConfigurationIndex, see TS 36.211 (5.7.1). \vr{[0..63]}
  
  uint8_t prach_ConfigIndex;
  /// Parameter: High-speed-flag, see TS 36.211 (5.7.2). \vr{[0..1]} 1 corresponds to Restricted set and 0 to Unrestricted set.
  uint8_t highSpeedFlag;
  /// Parameter: \f$N_\text{CS}\f$, see TS 36.211 (5.7.2). \vr{[0..15]}\n Refer to table 5.7.2-2 for preamble format 0..3 and to table 5.7.2-3 for preamble format 4.
  uint8_t zeroCorrelationZoneConfig;
  /// Parameter: prach-FrequencyOffset, see TS 36.211 (5.7.1). \vr{[0..94]}\n For TDD the value range is dependent on the value of \ref prach_ConfigIndex.
  uint8_t prach_FreqOffset;

  uint16_t pad0;

}UE_UL_TYPE1_PRACH;

typedef struct UE_UL_TYPE1_PUCCH_C
{
  uint16_t RNTI;
  uint16_t UlStates;
  uint16_t UlChSel;
  uint16_t PGType;
  uint16_t NumofNP;
  uint16_t cqiInfoLen;
  uint16_t nPucchIndex;
  uint16_t deltaPUCCHshift;
  uint16_t betaPUCCH;
  uint16_t TA;
  uint16_t Subfn;
  uint16_t Isrs;
  uint16_t SRSDuration;
  uint16_t Bsrs;
  uint16_t Nra;
  uint16_t Ktc;
  uint16_t Bhop;
  uint16_t nRRC;
  uint16_t nSRScs;
  uint16_t betaSRS;
} UE_UL_TYPE1_PUCCH_C;

typedef struct UE_UL_TYPE1_PUCCH_D
{
  uint16_t RNTI;
  uint16_t UlChSel;
  uint16_t SR;
  uint16_t HARQ;
  uint16_t CQI;
  uint16_t padding;
} UE_UL_TYPE1_PUCCH_D;
typedef struct UE_UL_TYPE1_PUSCH_C
{
  uint16_t RNTI;
  uint16_t UlStates;
  uint16_t UlChSel;
  uint16_t PGType;
  uint16_t NumofNP;
  uint16_t PrbStart;
  uint16_t NumPrb;
  uint16_t PuschHopFlag;
  uint16_t ULHop;
  uint16_t puschHopOffset;
  uint16_t Qm;
  uint16_t rvIdx;
  uint16_t dmrs2;
  uint16_t harqInfoLen;
  uint16_t harqOffset;
  uint16_t Nbundled;
  uint16_t riInfoLen;
  uint16_t riOffset;
  uint16_t cqiInfoLen;
  uint16_t cqiOffset;
  uint16_t betaPUSCH;
  uint16_t ndi;
  uint16_t CurrentTxNB;
  uint16_t Nsb;
  uint16_t TA;
  uint16_t Subfn;
  uint16_t Isrs;
  uint16_t SRSDuration;
  uint16_t Bsrs;
  uint16_t Nra;
  uint16_t Ktc;
  uint16_t Bhop;
  uint16_t nRRC;
  uint16_t nSRScs;
  uint16_t betaSRS;
  uint16_t padding;
  uint32_t tbSize;
} UE_UL_TYPE1_PUSCH_C;

typedef struct UE_UL_TYPE1_PUSCH_D
{
	uint32_t RACH_FLAG;  //yihuan add 20180620 , 1 as msg1 , 3 as msg3 , 0 as normal data
  uint16_t RNTI;
	uint16_t UlChSel;
	uint16_t CQI;
	uint16_t RI;
	uint32_t HARQ_ACK;

  //yihuan add 20180625
  uint32_t countall;
}UE_UL_TYPE1_PUSCH_D;

////////////////////////////////////////type2 ue to enb uplink start///////////////////////////////////////////////////
typedef struct ENB_UL_TYPE2_PUBLIC_C
{
	uint16_t UserNum;
	uint16_t PRACHOffset;  //yihuan add 20180612
	uint16_t PUCCHCOffset;
	uint16_t PUSCHCOffset;
	uint16_t PUSCHDOffset;
}ENB_UL_TYPE2_PUBLIC_C;

typedef struct ENBULPHYtoPHYADPType2
{
	GeneralHeader12 GHead;
	ENB_UL_TYPE2_PUBLIC_C UL_TYPE2_PUBLIC_C;
}ENBULPHYtoPHYADPType2;

typedef struct ENB_UL_TYPE2_PRACH
{
	uint16_t ra_RNTI;
	uint8_t  ra_PreambleIndex;
	uint16_t timing_offset;
}ENB_UL_TYPE2_PRACH;

typedef struct ENB_UL_TYPE2_PUCCH_C
{
	uint16_t rnti;
	uint16_t UlChSel;
	uint16_t AckNack;
	uint16_t SR;
	uint16_t cqi;

	/****FPGA提供****/
	uint16_t TA;
	uint16_t RAPID;
	uint16_t RARNTI;
	uint16_t RAmaskindex;
	/****FPGA提供****/
	uint16_t padding;
}ENB_UL_TYPE2_PUCCH_C;

typedef struct ENB_UL_TYPE2_PUSCH_C
{
	uint16_t rnti;
	uint16_t UlChSel;
	uint16_t NumofNP;
	uint16_t CrcCheck;
	uint16_t AckNackBitsInfo;
	uint16_t CqiBitInfo;
	uint16_t RiBitInfo;
	/****FPGA提供****/
	uint16_t TA;
	uint16_t RAPID;
	uint16_t RARNTI;
	uint16_t RAmaskindex;
	/****FPGA提供****/
	uint16_t padding;
}ENB_UL_TYPE2_PUSCH_C;

typedef struct ENB_UL_TYPE2_PUSCH_D
{
	uint32_t rach_flag;     //yihuan add 20180614 msg1 = 1 msg3 = 3 normaldata = 0
	uint16_t rnti; 
	uint16_t UlChSel;
	uint32_t datalen;//数据长度
}ENB_UL_TYPE2_PUSCH_D;
#pragma pack()
////////////////////////////////////////type2 ue to enb uplink end///////////////////////////////////////////////////